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    uvm_reg_array / uvm_reg_array_md 文件删除（UVM_SPARSE_ARRAY 扩展终止）

    编译断点

    影响范围

    构建定义 UVM_SPARSE_ARRAY 或引用旧 reg_array 类型/成员。

    具体差异

    该稀疏数组寄存器是 VCS/Synopsys 私有扩展（Accellera 1.2/2.0 均无），默认不开启。1.2 下定义 +define+UVM_SPARSE_ARRAY 可用；2.0 下定义该宏会因找不到文件而编译失败。随动的 uvm_reg_file::get_size/get_default_reg/Xlock_modelX（1.2 uvm_reg_file.svh:120/:127/:134，为 reg_array 服务）一并移除。

    修改方案

    若环境定义了 UVM_SPARSE_ARRAY，需移除该 define 并改用普通 uvm_reg 数组建模。

    兼容措施与范围：兼容措施不恢复稀疏 reg 数组扩展；移除开关后仍须完整迁移模型与地址映射。

    迁移后验证

    去掉旧库 include 依赖并编译普通 reg 数组模型；检查地址映射、元素访问和实际资源消耗，不能只删 define 后省略原模型。

    记录本条结果：M07-018 · 状态与证据。

    补充查阅

    扫描定位与记录结果

    有扫描规则，覆盖部分可识别写法。脚本检查名称、参数和部分 FLAG 表达式，并对少数直接声明关联使用点；未做完整类型解析或预处理，行为结果仍需验证。

    • D3 · 文本匹配：UVM_SPARSE_ARRAY / uvm_reg_array（VCS 私有扩展，2.0 悬空引用编译失败）。
    1
    uv run tools/uvm_migration_scan.py <SoC代码目录> --rules D3

    核对命中对象及生效分支后，在条目清单记录修改与验证证据；扫描规则记录用于整理命中位置。

    扫描器下载、输入范围与报告说明

    源码与标准依据

    核查方式：源码核对。未单独进行 VCS 行为实测。

    VCS 内置 UVM-1.2：uvm_reg_array.svh:35、uvm_reg_array_md.svh:35；由 uvm_reg_model.svh:436 的 `ifdef UVM_SPARSE_ARRAY 包入

    VCS 内置 uvm-ieee-2020-2.0：文件已删除；uvm_reg_model.svh:449-uvm_reg_model.svh:451 仍残留 `ifdef UVM_SPARSE_ARRAY 的 include（悬空引用）

    引用代码（高亮为引用行）；上方行号链接可直接定位。

    src/vcs-uvm-1.2/reg/uvm_reg_array.svh
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    // It optimizes the memory by allocating memory for only
// registers which are actually accessed during simulation
//
virtual class uvm_reg_array extends uvm_reg_file;

   rand local uvm_reg      ral_regs[uvm_reg_addr_t];
   local uvm_reg           m_default_reg;
   local uvm_reg_addr_t    m_size;
   local uvm_reg_addr_t    m_inter_register_offset;
   local string            m_hdl_path;
   local bit               m_locked;
   //local uvm_reg_block     parent;
   //local uvm_reg_file   m_rf;
   //local string            default_hdl_path = "RTL";
   //local uvm_object_string_pool #(uvm_queue #(string)) hdl_paths_pool;


   //----------------------
   // Group: Initialization

    完整源码 · SHA256：c4abd87d3007c01b5c7ad603e9e6dd263de9aafd1cc2db74cf73f24d169cc028

    src/vcs-uvm-1.2/reg/uvm_reg_array_md.svh
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    // It optimizes the memory by allocating memory for only
// registers which are actually accessed during simulation
//
virtual class uvm_reg_array_md extends uvm_reg_file;

   rand local uvm_reg      ral_regs[uvm_reg_addr_t];
   local uvm_reg           m_default_reg;
   local int unsigned      m_dimensions;
   local uvm_reg_addr_t    m_size[];
   local uvm_reg_addr_t    m_inter_register_offsets[];
   local uvm_reg_addr_t    m_corrected_offsets[];
   local string            m_hdl_path;
   local bit               m_locked;
   local bit               m_offset_corrected;
   //local uvm_reg_block     parent;
   //local uvm_reg_file   m_rf;
   //local string            default_hdl_path = "RTL";
   //local uvm_object_string_pool #(uvm_queue #(string)) hdl_paths_pool;

    完整源码 · SHA256：e68ea6c068d9067ab0586ba601741984b8e20f846a853ad3fd7a89215e55315f

    src/vcs-uvm-1.2/reg/uvm_reg_model.svh
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    `include "reg/uvm_mem.svh"
`include "reg/uvm_reg_map.svh"
`include "reg/uvm_reg_block.svh"
`ifdef UVM_SPARSE_ARRAY
`include "reg/uvm_reg_array.svh"
`include "reg/uvm_reg_array_md.svh"
`endif

`include "reg/sequences/uvm_reg_hw_reset_seq.svh"
`include "reg/sequences/uvm_reg_bit_bash_seq.svh"
`include "reg/sequences/uvm_mem_walk_seq.svh"
`include "reg/sequences/uvm_mem_access_seq.svh"
`include "reg/sequences/uvm_reg_access_seq.svh"
`include "reg/sequences/uvm_reg_mem_shared_access_seq.svh"
`include "reg/sequences/uvm_reg_mem_built_in_seq.svh"
`include "reg/sequences/uvm_reg_mem_hdl_paths_seq.svh"

`include "reg/snps_uvm_reg_bank.svh"

    完整源码 · SHA256：f29457c271b91936df38d49968f1b68383159bc266e9858e32a4fe3af4fded8d

    src/vcs-uvm-ieee-2020-2.0/reg/uvm_reg_model.svh
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    `include "reg/uvm_mem.svh"
`include "reg/uvm_reg_map.svh"
`include "reg/uvm_reg_block.svh"
`ifdef UVM_SPARSE_ARRAY
`include "reg/uvm_reg_array.svh"
`include "reg/uvm_reg_array_md.svh"
`endif

`include "reg/sequences/uvm_reg_randval.svh"
`include "reg/sequences/uvm_reg_hw_reset_seq.svh"
`include "reg/sequences/uvm_reg_bit_bash_seq.svh"
`include "reg/sequences/uvm_mem_walk_seq.svh"
`include "reg/sequences/uvm_mem_access_seq.svh"
`include "reg/sequences/uvm_reg_access_seq.svh"
`include "reg/sequences/uvm_reg_mem_shared_access_seq.svh"
`include "reg/sequences/uvm_reg_mem_built_in_seq.svh"
`include "reg/sequences/uvm_reg_mem_hdl_paths_seq.svh"

`include "reg/snps_uvm_reg_bank.svh"

`endif // UVM_REG_MODEL__SV

    完整源码 · SHA256：14112c26926a565dcc1015ad016048c30900829ae7de1621707e404f72c57901

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