if(has_reset)set_reset(reset);elseuvm_resource_db#(bit)::set({"REG::",get_full_name()},"NO_REG_HW_RESET_TEST",1);m_parent.add_field(this);if(!m_policy_names.exists(m_access))begin`uvm_error("RegModel",{"Access policy '",access,"' for field '",get_full_name(),"' is not defined. Setting to RW"})m_access="RW";endif(size>m_max_size)m_max_size=size;// Ignore is_rand if the field is known not to be writeable
if(uvm_resource_db#(bit)::get_by_name({"REG::",blk.get_full_name()},"NO_REG_TESTS",0)!=null||uvm_resource_db#(bit)::get_by_name({"REG::",blk.get_full_name()},"NO_REG_HW_RESET_TEST",0)!=null)beginreturn;endblk.get_maps(maps);// Iterate over all maps defined for the RegModel blockforeach(maps[d])beginuvm_regregs[$];`ifdefUVM_REG_FIELD_LEVEL_ATTRIBUTEuvm_reg_fieldfields[$];uvm_check_efields_to_suppress[uvm_reg_field];`endifmaps[d].get_submaps(sub_maps);
if(uvm_resource_db#(bit)::get_by_name({"REG::",regs[i].get_full_name()},"NO_REG_TESTS",0)!=null||uvm_resource_db#(bit)::get_by_name({"REG::",regs[i].get_full_name()},"NO_REG_HW_RESET_TEST",0)!=null)continue;`ifdefUVM_REG_FIELD_LEVEL_ATTRIBUTE// Need to iterate over fields to mark fields for not comparingregs[i].get_fields(fields);foreach(fields[k])beginif(uvm_resource_db#(bit)::get_by_name({"REG::",fields[k].get_full_name()},{fields[k].get_full_name(),"_NO_REG_TESTS"},0)!=null||uvm_resource_db#(bit)::get_by_name({"REG::",fields[k].get_full_name()},{fields[k].get_full_name(),"_NO_REG_HW_RESET_TEST"},0)!=null)beginfields_to_suppress[fields[k]]=fields[k].get_compare();fields[k].set_compare(UVM_NO_CHECK);endendfields.delete();`endif`uvm_info(get_type_name(),$sformatf("Verifying reset value of register %s in map \"%s\"...",regs[i].get_full_name(),maps[d].get_full_name()),UVM_LOW);regs[i].mirror(status,UVM_CHECK,UVM_FRONTDOOR,maps[d],this);if(status!=UVM_IS_OK)begin`uvm_error(get_type_name(),
foreach(regs[ridx])beginif(uvm_resource_db#(bit)::get_by_name({"REG::",regs[ridx].get_full_name()},"NO_REG_TESTS",0)!=null||regs[ridx].has_reset()==0||uvm_resource_db#(bit)::get_by_name({"REG::",regs[ridx].get_full_name()},"NO_REG_HW_RESET_TEST",0)!=null)continue;beginuvm_reg_maprm[$];uvm_status_estatus;uvm_reg_fieldfields[$];uvm_check_efield_check_restore[uvm_reg_field];regs[ridx].get_maps(rm);regs[ridx].get_fields(fields);foreach(fields[fidx])beginif(fields[fidx].has_reset()==0||fields[fidx].get_compare()==UVM_NO_CHECK||uvm_resource_db#(bit)::get_by_name({"REG::",fields[fidx].get_full_name()},"NO_REG_HW_RESET_TEST",0)!=null)beginfield_check_restore[fields[fidx]]=fields[fidx].get_compare();fields[fidx].set_compare(UVM_NO_CHECK);endend// if there are some fields to checkif(fields.size()!=field_check_restore.size())beginforeach(rm[midx])begin`uvm_info(get_type_name(),$sformatf("Verifying reset value of register %s in map \"%s\"...",regs[ridx].get_full_name(),rm[midx].get_full_name()),UVM_LOW)regs[ridx].mirror(status,UVM_CHECK,UVM_FRONTDOOR,rm[midx],this);