`timescale 1ns/1ps
`include "uvm_macros.svh"
import uvm_pkg::*;
class reset_probe_reg extends uvm_reg;
uvm_reg_field reset_field, no_reset_field;
int mirror_calls;
bit unchecked_no_reset;
function new(string name="reg"); super.new(name,32,UVM_NO_COVERAGE); endfunction
function void build(uvm_reg_block parent);
configure(parent);
reset_field = new("reset_field"); no_reset_field = new("no_reset_field");
reset_field.configure(this,16,0,"RW",0,0,1,1,0);
no_reset_field.configure(this,16,16,"RW",0,0,0,1,0);
endfunction
virtual task mirror(output uvm_status_e status, input uvm_check_e check=UVM_NO_CHECK,
`ifdef REVIEW_UVM20
input uvm_door_e path=UVM_DEFAULT_DOOR,
`else
input uvm_path_e path=UVM_DEFAULT_PATH,
`endif
input uvm_reg_map map=null, input uvm_sequence_base parent=null,
input int prior=-1, input uvm_object extension=null, input string fname="", input int lineno=0);
mirror_calls++;
unchecked_no_reset = no_reset_field.get_compare() == UVM_NO_CHECK;
status = UVM_IS_OK;
endtask
endclass
class reset_probe_block extends uvm_reg_block;
function new(string name="block"); super.new(name,UVM_NO_COVERAGE); endfunction
endclass
module reset_sequence_probe;
initial begin
reset_probe_block root_value = new("root_value"), child_value = new("child_value"), leaf_value = new("leaf_value");
reset_probe_reg register_value = new();
uvm_reg_hw_reset_seq sequence_value = new();
uvm_reg_map map;
child_value.configure(root_value);
leaf_value.configure(child_value);
register_value.build(leaf_value);
map = leaf_value.create_map("map",0,4,UVM_LITTLE_ENDIAN);
map.add_reg(register_value,0);
root_value.lock_model();
sequence_value.model = root_value;
sequence_value.start(null);
$display("REVIEW|leaf_mirror_calls|%0d", register_value.mirror_calls);
$display("REVIEW|no_reset_unchecked_during_mirror|%0d", register_value.unchecked_no_reset);
$display("REVIEW|compare_restored|%0d", register_value.no_reset_field.get_compare() == UVM_CHECK);
$display("REVIEW|done|1");
$finish;
end
endmodule